High-speed analog-to-digital converter (ADC) front-ends in serial link receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as 4-level pulse amplitude modulation (PAM4) and duo-binary. These ADC-based serial link receivers are becoming more popular as they allow for more complex and flexible back-end digital signal processing as compared to binary or mixed-signal receivers. The power consumption, however, of these ADC front-ends and subsequence digital signal processing is a major design issue.
One of the main factors in power consumption is the resolution of the high-speed ADC. Much research has been performed to determine both the ADC resolution for optimal performance per power and the channel equalization techniques performed by the subsequent digital signal processor (DSP). The choice of ADC resolution is further complicated by the various channel applications. In general, as channel attenuation becomes worse, a higher resolution ADC is needed. For example, a 6˜8 bit ADC resolution is suitable for use with equalization techniques for long channel (e.g., 25˜30 decibels (dB)) applications. A conventional high-speed ADC provides digital output having a single resolution, which is inflexible and does not allow for optimal balancing of performance and power consumption across channel applications and channel equalization techniques.